Commit 95d27008 authored by Mikaël BRIDAY's avatar Mikaël BRIDAY
Browse files

broche CS du TFT maj

parent 9be173fd
#include "spi.h"
#include "stm32f3xx.h"
//use SPI1:
// use SPI1:
// CS MCP : PA11 (I/O) - Arduino D10
// CS TFT : PA2 (I/O) - Arduino A7
// CS TFT : PA4 (I/O) - Arduino A3
// MOSI: PB5 (AF5) - Arduino D11
// MISO: PB4 (AF5) - Arduino D12
// SCK : PB3 (AF5) - Arduino D13
void setupSPI()
{
//1 - input clock = 64MHz.
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
__asm("nop");
//reset peripheral (mandatory!)
RCC->APB2RSTR |= RCC_APB2RSTR_SPI1RST;
RCC->APB2RSTR &= ~RCC_APB2RSTR_SPI1RST;
//init procedure p.962 - section 30.5.7
//2 - GPIOs
RCC->AHBENR |= RCC_AHBENR_GPIOAEN | //clock for GPIOA
RCC_AHBENR_GPIOBEN; //clock for GPIOB
__asm("nop"); //wait until GPIOx clock is Ok.
GPIOB->OSPEEDR = 3 << GPIO_OSPEEDER_OSPEEDR3_Pos |
3 << GPIO_OSPEEDER_OSPEEDR4_Pos |
3 << GPIO_OSPEEDER_OSPEEDR5_Pos ;
GPIOA->MODER |= 1 << GPIO_MODER_MODER11_Pos| //PA11 output (CS)
1 << GPIO_MODER_MODER2_Pos; //PA2 output (CS)
GPIOB->AFR[0] |= 5 << GPIO_AFRL_AFRL3_Pos| //alternate func AF5
5 << GPIO_AFRL_AFRL4_Pos| //for 3 pins
5 << GPIO_AFRL_AFRL5_Pos;
GPIOB->MODER |= 2 << GPIO_MODER_MODER3_Pos| //alternate function
2 << GPIO_MODER_MODER4_Pos| //for these 3 pins
2 << GPIO_MODER_MODER5_Pos;
GPIOB->PUPDR |= 1 << GPIO_PUPDR_PUPDR3_Pos | //pull-up...
1 << GPIO_PUPDR_PUPDR4_Pos |
1 << GPIO_PUPDR_PUPDR5_Pos ;
//3 - Write the CR1 register
SPI1->CR1 = SPI_CR1_BR_1 | //fPCLK/8 => 8MHz (max 10MHz)
//SPI_CR1_BR_2 | //fPCLK/128 => 0.5MHz (tmp)
SPI_CR1_MSTR ; //master mode
SPI1->CR2 = 0x7 << SPI_CR2_DS_Pos | //select 8 bits
SPI_CR2_FRXTH | //Fifo RX threshold 8-bits
SPI_CR2_SSOE;
SPI1->CR1 |= SPI_CR1_SPE ; //spi enabled
void setupSPI() {
// 1 - input clock = 64MHz.
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
__asm__("nop");
// reset peripheral (mandatory!)
RCC->APB2RSTR |= RCC_APB2RSTR_SPI1RST;
RCC->APB2RSTR &= ~RCC_APB2RSTR_SPI1RST;
// init procedure p.962 - section 30.5.7
// 2 - GPIOs
RCC->AHBENR |= RCC_AHBENR_GPIOAEN | // clock for GPIOA
RCC_AHBENR_GPIOBEN; // clock for GPIOB
__asm__("nop"); // wait until GPIOx clock is Ok.
GPIOB->OSPEEDR = 3 << GPIO_OSPEEDER_OSPEEDR3_Pos |
3 << GPIO_OSPEEDER_OSPEEDR4_Pos |
3 << GPIO_OSPEEDER_OSPEEDR5_Pos;
GPIOA->MODER |= 1 << GPIO_MODER_MODER11_Pos | // PA11 output (CS)
1 << GPIO_MODER_MODER4_Pos; // PA4 output (CS)
GPIOB->AFR[0] |= 5 << GPIO_AFRL_AFRL3_Pos | // alternate func AF5
5 << GPIO_AFRL_AFRL4_Pos | // for 3 pins
5 << GPIO_AFRL_AFRL5_Pos;
GPIOB->MODER |= 2 << GPIO_MODER_MODER3_Pos | // alternate function
2 << GPIO_MODER_MODER4_Pos | // for these 3 pins
2 << GPIO_MODER_MODER5_Pos;
GPIOB->PUPDR |= 1 << GPIO_PUPDR_PUPDR3_Pos | // pull-up...
1 << GPIO_PUPDR_PUPDR4_Pos | 1 << GPIO_PUPDR_PUPDR5_Pos;
// 3 - Write the CR1 register
SPI1->CR1 = SPI_CR1_BR_1 | // fPCLK/8 => 8MHz (max 10MHz)
// SPI_CR1_BR_2 | //fPCLK/128 => 0.5MHz (tmp)
SPI_CR1_MSTR; // master mode
SPI1->CR2 = 0x7 << SPI_CR2_DS_Pos | // select 8 bits
SPI_CR2_FRXTH | // Fifo RX threshold 8-bits
SPI_CR2_SSOE;
SPI1->CR1 |= SPI_CR1_SPE; // spi enabled
}
void beginTransaction()
{
volatile uint16_t __attribute__((unused)) tmp;
//while(SPI1->SR & SPI_SR_BSY);
//while(SPI1->SR & SPI_SR_RXNE) //fifo not empty
// tmp = SPI1->DR; //empty the Rx fifo
GPIOA->BSRR = GPIO_BSRR_BR_11; //CS=0
void beginTransaction() {
volatile uint16_t __attribute__((unused)) tmp;
// while(SPI1->SR & SPI_SR_BSY);
// while(SPI1->SR & SPI_SR_RXNE) //fifo not empty
// tmp = SPI1->DR; //empty the Rx fifo
GPIOA->BSRR = GPIO_BSRR_BR_11; // CS=0
}
void endTransaction()
{
while(SPI1->SR & SPI_SR_BSY);
GPIOA->BSRR = GPIO_BSRR_BS_11; //CS=1
void endTransaction() {
while (SPI1->SR & SPI_SR_BSY)
;
GPIOA->BSRR = GPIO_BSRR_BS_11; // CS=1
}
//low speed transfer:
// low speed transfer:
// * wait until fifo is not full
// * send data
// * be sure that transfer is complete
// * and return the last value.
uint8_t transfer8(uint8_t val)
{
volatile uint16_t __attribute__((unused)) tmp;
volatile SPI_TypeDef *__attribute((unused)) spi=SPI1;
while(SPI1->SR & SPI_SR_BSY);
while(SPI1->SR & SPI_SR_RXNE) //fifo not empty
tmp = (uint16_t)SPI1->DR; //empty the Rx fifo
*(__IO uint8_t *)&SPI1->DR = val;
while(!(SPI1->SR & SPI_SR_RXNE));
return *(__IO uint8_t *)&SPI1->DR;
uint8_t transfer8(uint8_t val) {
volatile uint16_t __attribute__((unused)) tmp;
volatile SPI_TypeDef *__attribute((unused)) spi = SPI1;
while (SPI1->SR & SPI_SR_BSY)
;
while (SPI1->SR & SPI_SR_RXNE) // fifo not empty
tmp = SPI1->DR; // empty the Rx fifo
*(__IO uint8_t *)&SPI1->DR = val;
while (SPI1->SR & SPI_SR_BSY)
;
// while(!(SPI1->SR & SPI_SR_RXNE));
return *(__IO uint8_t *)&SPI1->DR;
}
//higher speed write transfer (than transfer8)
// higher speed write transfer (than transfer8)
// * wait until TX fifo is not full
// * send data
void write8(uint8_t val)
{
//Fifo tx level full?
while(((SPI1->SR & SPI_SR_FTLVL_Msk) >> SPI_SR_FTLVL_Pos) == 3);
*(__IO uint8_t *)&SPI1->DR = val;
void write8(uint8_t val) {
// Fifo tx level full?
while (((SPI1->SR & SPI_SR_FTLVL_Msk) >> SPI_SR_FTLVL_Pos) == 3)
;
*(__IO uint8_t *)&SPI1->DR = val;
}
......@@ -8,8 +8,8 @@
#define SPI_DC_HIGH() {GPIOA->BSRR = GPIO_BSRR_BS_12;}
#define SPI_DC_LOW() {GPIOA->BSRR = GPIO_BSRR_BR_12;}
#define SPI_CS_HIGH() {GPIOA->BSRR = GPIO_BSRR_BS_2;}
#define SPI_CS_LOW() {GPIOA->BSRR = GPIO_BSRR_BR_2;}
#define SPI_CS_HIGH() {GPIOA->BSRR = GPIO_BSRR_BS_4;}
#define SPI_CS_LOW() {GPIOA->BSRR = GPIO_BSRR_BR_4;}
/*
* Software SPI Macros
......@@ -77,36 +77,47 @@
// #define SPI_MAX_PIXELS_AT_ONCE 32
// #define HSPI_WRITE_PIXELS(c,l) SPI_OBJECT.writePixels(c,l)
// #else
// #define HSPI_WRITE_PIXELS(c,l) for(uint32_t i=0; i<((l)/2); i++){ SPI_WRITE16(((uint16_t*)(c))[i]); }
// #define HSPI_WRITE_PIXELS(c,l) for(uint32_t i=0; i<((l)/2); i++){
// SPI_WRITE16(((uint16_t*)(c))[i]); }
// #endif
//#else
// // Standard Byte-by-Byte SPI
//
// #if defined (__AVR__) || defined(TEENSYDUINO)
//static inline uint8_t _avr_spi_read(void) __attribute__((always_inline));
//static inline uint8_t _avr_spi_read(void) {
// static inline uint8_t _avr_spi_read(void) __attribute__((always_inline));
// static inline uint8_t _avr_spi_read(void) {
// uint8_t r = 0;
// SPDR = r;
// while(!(SPSR & _BV(SPIF)));
// r = SPDR;
// return r;
//}
// #define HSPI_WRITE(b) {SPDR = (b); while(!(SPSR & _BV(SPIF)));}
// #define HSPI_READ() _avr_spi_read()
// #define HSPI_WRITE(b) {SPDR = (b); while(!(SPSR &
// _BV(SPIF)));} #define HSPI_READ() _avr_spi_read()
// #else
#define HSPI_WRITE(b) transfer8((uint8_t)(b))
#define HSPI_READ() transfer8((uint8_t)(0))
#define HSPI_WRITE(b) transfer8((uint8_t)(b))
#define HSPI_READ() transfer8((uint8_t)(0))
// #endif
#define HSPI_WRITE16(s) HSPI_WRITE((s) >> 8); HSPI_WRITE(s)
#define HSPI_WRITE32(l) HSPI_WRITE((l) >> 24); HSPI_WRITE((l) >> 16); HSPI_WRITE((l) >> 8); HSPI_WRITE(l)
#define HSPI_WRITE_PIXELS(c,l) for(uint32_t i=0; i<(l); i+=2){ HSPI_WRITE(((uint8_t*)(c))[i+1]); HSPI_WRITE(((uint8_t*)(c))[i]); }
#define HSPI_WRITE16(s) \
HSPI_WRITE((s) >> 8); \
HSPI_WRITE(s)
#define HSPI_WRITE32(l) \
HSPI_WRITE((l) >> 24); \
HSPI_WRITE((l) >> 16); \
HSPI_WRITE((l) >> 8); \
HSPI_WRITE(l)
#define HSPI_WRITE_PIXELS(c, l) \
for (uint32_t i = 0; i < (l); i += 2) { \
HSPI_WRITE(((uint8_t *)(c))[i + 1]); \
HSPI_WRITE(((uint8_t *)(c))[i]); \
}
//#endif
#define SPI_BEGIN() setupSPI();
#define SPI_BEGIN_TRANSACTION()
#define SPI_END_TRANSACTION()
#define SPI_WRITE16(s) HSPI_WRITE16(s);
#define SPI_WRITE32(l) HSPI_WRITE32(l);
#define SPI_WRITE_PIXELS(c,l) HSPI_WRITE_PIXELS(c,l);
#define SPI_BEGIN() setupSPI();
#define SPI_BEGIN_TRANSACTION()
#define SPI_END_TRANSACTION()
#define SPI_WRITE16(s) HSPI_WRITE16(s);
#define SPI_WRITE32(l) HSPI_WRITE32(l);
#define SPI_WRITE_PIXELS(c, l) HSPI_WRITE_PIXELS(c, l);
#endif // _ADAFRUIT_SPITFT_MACROS
# define CPU OPTIONS
set(CPU_OPTIONS -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -DSTM32F303x8 -DARMCM4)
#set(CPU_OPTIONS -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -DSTM32F303x8 -DARMCM4)
set(CPU_OPTIONS -mthumb -mcpu=cortex-m4 -mfloat-abi=soft -DSTM32F303x8 -DARMCM4)
set(CMAKE_C_FLAGS_DEBUG "-O0 -g -Wall -fexceptions -Wno-deprecated -DDEBUG")
set(CMAKE_CXX_FLAGS_DEBUG "-O0 -g -Wall -fexceptions -Wno-deprecated -DDEBUG")
......
......@@ -66,8 +66,8 @@ extern void _start (void) __attribute__((noreturn)); /* PreeMain (C library
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void Default_Handler(void) ;
void Reset_Handler (void) ;
void Default_Handler(void) __attribute__ ((noreturn));
void Reset_Handler (void) __attribute__ ((noreturn));
/*----------------------------------------------------------------------------
......@@ -152,7 +152,7 @@ void FPU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
*----------------------------------------------------------------------------*/
extern const pFunc __Vectors[240];
const pFunc __Vectors[240] __attribute__ ((section(".vectors"))) = {
(pFunc)((int)(&__StackTop)), /* Initial Stack Pointer */
(pFunc)(&__StackTop), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
......@@ -281,6 +281,10 @@ void Reset_Handler(void) {
pDest = &__bss_start__;
while(pDest < &__bss_end__ ) *pDest++ = 0UL;
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
SystemInit(); /* CMSIS System Initialization */
_start(); /* Enter PreeMain (C library entry point) */
}
......
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